The present invention relates to integrated circuits using CMOS voltage signal levels, and more particularly, to a duty cycle controlled CML-CMOS converter, and also to a first amplification stage therefor.
The use of CML and CMOS technologies in a single integrated circuit (IC) requires a conversion of CML differential voltage levels to CMOS compatible voltage levels. CML voltage levels represent the two values of a data bit depending on which of the two levels is more positive than the other. A typical CML circuit operates with a differential swing of two to three hundred milliVolts, but smaller and larger swings are possible. In contrast, a typical CMOS circuit operates according to a single ended voltage, with two specified voltage ranges with respect to that defining the two values of a data bit.
Conventional techniques of CML to CMOS conversion are found to be lacking for high speed applications, and due to problems arising from the statistical variation of small devices. Thus there is a need for an improved CML-CMOS converter.